Lead Validation Engineer – BMS

We are looking for a Lead Validation Engineer to head the BMS validation function for EV, ESS, and Telecom Power products. The role owns the end-to-end validation strategy, drives the HIL and lab roadmap, manages a team of test engineers, and is accountable for release quality, compliance, and customer facing validation deliverables.

1. Validation Leadership: Own the end-to-end validation strategy and roadmap for BMS products across EV, ESS, and Telecom platforms; define V&V approach, milestones, and release quality gates.

2. Team Management: Lead, mentor, and grow a team of validation engineers; allocate tasks, conduct performance reviews, and build technical capability across HIL, automation, and lab testing.

3. Test Architecture: Architect HIL, SIL, and bench test frameworks using NI (TestStand/VeriStand/LabVIEW), dSPACE, and Python; define reusable libraries, naming standards, and CI integration.

4. Test Planning & Traceability: Drive test plans, coverage matrices, and requirement-to-test traceability in JIRA/Polarion/DOORS; sign off entry/exit criteria for each release.

5. Functional & System Validation: Oversee verification of voltage/current sensing, SOC/SOH/SOP, cell balancing, contactor and precharge logic, isolation monitoring, and thermal management.

6. Protections & Abuse Testing: Govern over/under-voltage, over-current, over temperature, short-circuit, and thermal runaway test campaigns under fault and abuse conditions.

7. Communication & Diagnostics: Ensure complete coverage of CAN, CAN-FD, LIN, RS485, Modbus, UDS (ISO 14229), DTC handling, bootloader, and OTA update flows.

8. Compliance & Safety: Drive validation aligned with ISO 26262 (ASIL-B/C/D), IEC 61508, IEC 62619, AIS-156, UN R100, and UL 1973/9540A; contribute to FMEA, FTA, and safety case artifacts.

9. Lab & Infrastructure: Own the BMS lab roadmap including HIL benches, battery cyclers, power analyzers, and environmental chambers; plan capex, vendor selection, and capacity scaling.

10. Defect & Release Governance: Lead triage of critical defects, drive root cause analysis with firmware and hardware teams, and present release readiness to engineering leadership.

11. Stakeholder Management: Interface with product, systems, firmware, hardware, customers, and certification bodies during design reviews, audits, and field issue resolution.

12. Process & Continuous Improvement: Establish validation best practices, KPIs, and review cadences; drive automation coverage, regression efficiency, and lessons-learned across programs.

• Education
  Bachelor's or Master’s in Electrical, Electronics, Power Electronics, or Embedded Systems Engineering.
  
  BMS Expertise: Deep knowledge of master/slave BMS architecture, AFE ICs (LTC68xx, BQ79xx), Li-ion/LFP/NMC behavior, balancing, SOC/SOH algorithms, and pack-level integration.
  
  Tools & Scripting: Expert in Vector CANoe/CANalyzer, BusMaster, NI TestStand/VeriStand, dSPACE, INCA/CANape; strong in Python, CAPL, and C with automation frameworks.
  
  Standards: Working command of ISO 26262, IEC 61508, IEC 62619, AIS-156, UN R100, and UL 1973/9540A; experience supporting customer and certification audits.
  
  Leadership: Proven track record of leading validation teams of 4+ engineers, owning release sign-off, and managing cross-functional stakeholders in a product organization.

• Leadership ownership of the BMS validation function across EV, ESS, and telecom power product lines
• Strong influence on product quality, lab strategy, and engineering processes from day one
• Modern, well-equipped BMS lab with HIL benches, battery cyclers, and environmental chambers
• Collaborative engineering culture, clear growth path to engineering management, and competitive compensation